The invention relates to a semiconductor wafer with rear side identification having a multiplicity of information regarding the monocrystalline and surface and rear side constitution.
The rear side identification is introduced by the semiconductor wafer manufacturer on the rear side of the semiconductor wafer in order to reserve the top side of the semiconductor wafer for the active components and not to impair it by identification markings. Such identification markings would take up valuable semiconductor surface area and, the high quality of the semiconductor wafer top side reserved for active components can be impaired during the introduction of the marking. Such rear side identifications are introduced by etching technology and/or by laser writing techniques and are intended to make it possible to characterize the specific properties of the individual semiconductor wafers after various monocrystalline crystal growth methods, doping methods and/or after epitaxy methods where epitaxial layers are applied on the active top side by the semiconductor wafer manufacturer.
However, such information is lost during the process of thinning the semiconductor wafers since such thinning operations are effected from the rear side of the semiconductor wafer. However, there is a need to retain this information and additionally to store it and further process data added during the production of semiconductor device structures on the active top side of the semiconductor wafer.
The document U.S. Pat. No. 5,733,711 discloses a method in which both fixedly predefined and variable patterns can be formed independently of one another within a single photoresist layer. It is thus possible to form fixed general alignment marking patterns and a variable identification marking pattern in a single photoresist layer and both patterns are transferred to an underlying substrate by an individual etching process. In this case, each pattern formed is formed independently of the other by application of different reticle masks. The information that can be introduced by patterning of an individual photolithography layer or by etching with the aid of a photoresist mask on the top side of a semiconductor wafer is extremely limited and serves only for identification and/or alignment of the semiconductor wafer in the case of further photoresist layers. A pattern of this type is unable, however, to store information, in particular process information, and provide it for process analyses.
The document Lynn Dwyer et al., “Lithographic Chip Identification: Meeting the Failure Analysis Challenge”, SPIE Vol., Proceedings of Integrated Circuit Metrology, Inspection and Process Control IV, 1992, pages 615-629, discloses a method using step-by-step photolithography in which each individual semiconductor chip of a semiconductor wafer is identified in order to enable a subsequent fault analysis. A method of this type is complicated and takes up an additional region in which the identification is arranged for each semiconductor chip of a semiconductor wafer. This semiconductor chip marking is neither provided nor suitable for storing process information. Furthermore, there is also no provision made for preserving the rear side identification of the semiconductor wafer prior to destruction.
For these and other reasons, there is a need for the present invention.